Many computing devices (and other ICs) use multiple clock domains for various modules of the computing device. For instance, a data-transmitting module of a computing device might be operating in a first clock domain at a first clock frequency, while a data-receiving module of the computing device can be operating in a second clock domain at a second clock frequency. Furthermore, the second clock frequency may be asynchronously running relative to the first clock frequency.
Since the transmitting and receiving modules reside in different clock domains, the rate at which data is transmitted in one clock domain may not match the rate at which data is used in another clock domain. Thus, to accommodate for these rate differences, the prior art utilizes a first-in-first-out (“FIFO”) buffer in an interface to serve as a bridge for data to travel from one module in a first clock domain to another module in a second clock domain. Data can be clocked into the FIFO buffer according to a first clock signal of the first clock domain and clocked out of the FIFO buffer according to a second clock signal of the second clock domain.
The use of a FIFO buffer in the interface can cause a large amount of latency for transferring data between modules in different clock domains. In particular, space, power, and other resources can be expended by the FIFO buffer. Therefore, there exists a need to provide new methods and systems for interfacing clock domains that can account for any integral frequency difference, decrease latency, and reduce the amount of chip area and power used to implement such interface.